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TMS320TCI6482
Communications Infrastructure Digital Signal Processor
SPRS246F–APRIL 2005–REVISED MAY 2007
Table 8-58. McBSP 1 Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
COMMENTS
The CPU and EDMA
controller can only read
this register; they cannot
write to it.
0290 0000
DRR1
McBSP1 Data Receive Register via Configuration Bus
3400 0000
0290 0004
3400 0010
0290 0008
0290 000C
0290 0010
0290 0014
0290 0018
DRR1
DXR1
DXR1
SPCR1
RCR1
XCR1
SRGR1
MCR1
McBSP1 Data Receive Register via EDMA bus
McBSP1 Data Transmit Register via configuration bus
McBSP1 Data Transmit Register via EDMA bus
McBSP1 serial port control register
McBSP1 Receive Control Register
McBSP1 Transmit Control Register
McBSP1 sample rate generator register
McBSP1 multichannel control register
McBSP1 Enhanced Receive Channel Enable
Register 0 Partition A/B
McBSP1 Enhanced Transmit Channel Enable
Register 0 Partition A/B
McBSP1 Pin Control Register
McBSP1 Enhanced Receive Channel Enable
Register 1 Partition C/D
McBSP1 Enhanced Transmit Channel Enable
Register 1 Partition C/D
McBSP1 Enhanced Receive Channel Enable
Register 2 Partition E/F
McBSP1 Enhanced Transmit Channel Enable
Register 2 Partition E/F
McBSP1 Enhanced Receive Channel Enable
Register 3 Partition G/H
McBSP1 Enhanced Transmit Channel Enable
Register 3 Partition G/H
Reserved
0290 001C
RCERE01
0290 0020
XCERE01
0290 0024
PCR1
0290 0028
RCERE11
0290 002C
XCERE11
0290 0030
RCERE21
0290 0034
XCERE21
0290 0038
RCERE31
0290 003C
XCERE31
0290 0040 - 0293 FFFF
-
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