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8.19 UTOPIA
8.19.1 UTOPIA Device-Specific Information
8.19.2 UTOPIA Peripheral Register Description(s)
TMS320TCI6482
Communications Infrastructure Digital Signal Processor
SPRS246F–APRIL 2005–REVISED MAY 2007
The Universal Test and Operations PHY Interface for ATM (UTOPIA) peripheral is a 50 MHz, 8-Bit
Slave-only interface. The UTOPIA is more simplistic than the Ethernet MAC, in that the UTOPIA is
serviced directly by the EDMA3 controller. The UTOPIA peripheral contains two, two-cell FIFOs, one for
transmit and one for receive, with which to buffer up data sent/received across the pins. There is a
transmit and a receive event to the EDMA3 channel controller to enable servicing.
For more detailed information on the UTOPIA peripheral, see the
TMS320TCI648x DSP Universal Test &
Operations PHY Interface for ATM 2 (UTOPIA2)
(literature number
SPRU726
).
Table 8-104. UTOPIA Registers
HEX ADDRESS RANGE
02B4 0000
02B4 0004
02B4 0008
02B4 000C
02B4 0010
02B4 0014
02B4 0018
02B4 001C
02B4 0020 - 02B4 01FF
02B4 0200 - 02B7 FFFF
ACRONYM
UCR
-
-
-
-
CDR
EIER
EIPR
-
-
REGISTER NAME
UTOPIA Control Register
Reserved
Reserved
Reserved
Reserved
Clock Detect Register
Error Interrupt Enable Register
Error Interrupt Pending Register
Reserved
Reserved
Table 8-105. UTOPIA Data Queues (Receive and Transmit) Registers
HEX ADDRESS RANGE
3C00 0000 - 3C00 03FF
3C00 0400 - 3C00 07FF
ACRONYM
URQ
UXQ
REGISTER NAME
UTOPIA Receive (Rx) Data Queue
UTOPIA Transmit (Tx) Data Queue
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