
www.ti.com
8.10.4 HOLD/HOLDA Timing
HOLD
HOLDA
EMIF Bus
(A)
DSP Owns Bus
External Requestor
Owns Bus
DSP Owns Bus
DSP
DSP
1
3
2
5
4
AECLKOUT
TMS320TCI6482
Communications Infrastructure Digital Signal Processor
SPRS246F–APRIL 2005–REVISED MAY 2007
Table 8-48. Timing Requirements for the HOLD/HOLDA Cycles for EMIFA Module
(1)
(see
Figure 8-39
)
-850
A-1000
-1000
MIN
E
NO.
UNIT
MAX
3
t
h(HOLDAL-HOLDL)
E = the EMIF input clock (ECLKIN) period in ns for EMIFA.
Hold time, HOLD low after HOLDA low
ns
(1)
Table 8-49. Switching Characteristics Over Recommended Operating Conditions for the HOLD/HOLDA
Cycles for EMIFA Module
(1)(2)
(see
Figure 8-39
)
-850
A-1000
-1000
MIN
2E
0
2E
0
NO.
PARAMETER
UNIT
MAX
1
2
4
5
t
d(HOLDL-EMHZ)
t
d(EMHZ-HOLDAL)
t
d(HOLDH-EMLZ)
t
d(EMLZ-HOLDAH)
E = the EMIF input clock (ECLKIN) period in ns for EMIFA.
EMIFA Bus consists of: ACE[5:2], ABE[7:0], AED[63:0], AEA[19:0], ABA[1:0], AR/W, ASADS/ASRE, AAOE/ASOE, and AAWE/ASWE.
All pending EMIF transactions are allowed to complete before HOLDA is asserted. If no bus transactions are occurring, then the
minimum delay time can be achieved.
Delay time, HOLD low to EMIFA Bus high impedance
Delay time, EMIF Bus high impedance to HOLDA low
Delay time, HOLD high to EMIF Bus low impedance
Delay time, EMIFA Bus low impedance to HOLDA high
(3)
ns
ns
ns
ns
2E
7E
2E
(1)
(2)
(3)
A.
EMIFA Bus consists of: ACE[5:2], ABE[7:0], AED[63:0], AEA[19:0], ABA[1:0], AR/W, ASADS/ASRE, AAOE/ASOE,
and AAWE/ASWE.
Figure 8-39. HOLD/HOLDA Timing for EMIFA
168
C64x+ Peripheral Information and Electrical Specifications
Submit Documentation Feedback