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8.12.3 HPI Electrical Data/Timing
TMS320TCI6482
Communications Infrastructure Digital Signal Processor
SPRS246F–APRIL 2005–REVISED MAY 2007
Table 8-55. Timing Requirements for Host-Port Interface Cycles
(1)(2)
(see
Table 8-56
through
Figure 8-51
)
-850
A-1000
-1000
MIN
5
2
5
5
15
2M
5
5
5
1
0
NO.
UNIT
MAX
9
10
11
12
13
14
15
16
17
18
37
t
su(HASL-HSTBL)
t
h(HSTBL-HASL)
t
su(SELV-HASL)
t
h(HASL-SELV)
t
w(HSTBL)
t
w(HSTBH)
t
su(SELV-HSTBL)
t
h(HSTBL-SELV)
t
su(HDV-HSTBH)
t
h(HSTBH-HDV)
t
su(HCSL-HSTBL)
Setup time, HAS low before HSTROBE low
Hold time, HAS low after HSTROBE low
Setup time, select signals
(3)
valid before HAS low
Hold time, select signals
(3)
valid after HAS low
Pulse duration, HSTROBE low
Pulse duration, HSTROBE high between consecutive accesses
Setup time, select signals
(3)
valid before HSTROBE low
Hold time, select signals
(3)
valid after HSTROBE low
Setup time, host data valid before HSTROBE high
Hold time, host data valid after HSTROBE high
Setup time, HCS low before HSTROBE low
Hold time, HSTROBE low after HRDY low. HSTROBE should not be
inactivated until HRDY is active (low); otherwise, HPI writes will not
complete properly.
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
38
t
h(HRDYL-HSTBL)
1.1
ns
(1)
(2)
(3)
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
M = SYSCLK3 period = 6/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use M = 6 ns.
Select signals include: HCNTL[1:0] and HR/W. For HPI16 mode only, select signals also include HHWIL.
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C64x+ Peripheral Information and Electrical Specifications
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